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Careers

Inspiring, Empowering, Rewarding, Fun.

At Qloq Technologies, you will be part of a young and energetic team. You will get a chance to work on different interesting semiconductor solutions.
Qloq Technologies offers you a chance to gain experience in different design areas like Logic Design, Verification, Post-Validation.
Qloq Technologies promises to provide you with competitive compensation along with an attractive equity and other great benefits.

RTL/Logic Design Engineer

  1. Expertise in micro-architecture, design of design blocks(IP) to system-on-chip (SoC) components.
  2. one/more of the following system bus interfaces like PCI Express, USB, SATA, SDIO, MIPI and/or AMBA.
  3. Knowledge of SVA
  4. Knowledge of Memory Controllers, CPU Architecture is a plus.
  5. Knowledge of considerations for performance, power and cost optimization is desirable
  6. Good debugging and problem solving skills.
  7. Strong knowledge of Verilog
  8. Very good experience in writing scripts in Perl or Python or TCL.
  9. B.E/B.Tech, M.S/M.Tech with 2-10 years of experience.

 

Post-Validation Engineer

  1. Good understanding of Emulation tool .
  2. Manual and Automated regression/test runs.
  3. C/C++ based Test Case development experience for Emulation & Post-Silicon.
  4. Hands on with few of these protocols “SPI, I2C, UART, SDIO, PCIe,AMBA,AHB, Ethernet, USB2.0/3.0, DDR2/3”
  5. Test Suit development with OS or Bare Metal for Emulation, Post-Silicon.
  6. Experience with any of CPU like ARM/MIPS/MCU/Others with Trace32 /JTAG is required.
  7. Scripting knowledge with any of Tcl/Python/Unix-Shell.
  8. Use of good debugging methods on Emulation (e.g waveform analysis of trace captured) platforms.
  9. Hands on with lab equipments including Test pattern/traffic generator & analyzers .
  10. Knowledge of u-boot and other boot-loaders concept and application.
  11. Low level Assembly language programming skills.
  12. Board Bring up experience

 

Verification Engineer

  1. Develop verification testbench components for chip/module level using System Verilog, C & Perl
  2. Use high level language concepts (Object oriented, UVM/OVM/VMM etc) to develop extendable environment.
  3. Define and execute detailed verification plan from spec working with architects, designers, system engineers.
  4. Write tests, automate regression scripts and regression environment.
  5. Incorporate code-coverage, functional coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tapeout.
  6. Debug tests, run gate level simulations at unit/sdf delays
  7. Develop automated/scripted design flows for the above mentioned development processes
  8. Participate in FPGA/silicon debug and analysis
  9. Excellent debugging skills in both SW and ASIC hardware
  10. Must be proficient in Verilog (System Verilog preferred).
  11. Proficiency in scripting language like Perl, Tcl/Tk, Shell is a definite plus.
  12. Experience with simulators like ncVerilog (Incisive), VCS and QuestaSim.
  13. Good understanding of latest formal verification techniques, assertions, OOP etc is a plus.
  14. Understanding or prior experience with Industry standard protocols like USB, SPI, SATA, Ethernet, DisplayPort, SRIO etc is a definite plus
  15. BE/B.Tech, MS + 2-10 years of experience.

 

Physical Design Engineer

As a Physical Design Engineer, the ideal candidate will be responsible for handling all the aspects of Place & Route in RTL to GDSII implementation of complex ASICs using state of the art EDA tools. He should be an effective team player working closely with front end design as well as back end custom layout teams to deliver projects under tight schedule constraints.

Required Qualifications:

  • B.S/M.S in Electrical Engineering or related field with 2-10 Years of proven track record of independently delivering RTL to GDSII projects.
  • Experience in block & chip level floor planning, power grid design, Place & Route and physical verification.
  • Experience in working with analog IP, hard and soft macros and delivering hierarchical design projects.
  • Experience in Clock Tree Synthesis and Timing Closure
  • Experience in Scan & DFT
  • Experience in Power/Signal Integrity Analysis
  • Experience with Synopsys RTL to GDSII tool flow is a must.
  • Good scripting skills in C-Shell, Perl & Tcl
  • Must possess good written and verbal communication skills in order to work with teams across the globe
  • Experience in Logic Synthesis and STA
  • Experience with Mentor Graphics physical verification tools

 

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